|
IEEE 2011
PT11VL01
Design
and Characterization of Parallel Prefix Adders using FPGAs
IEEE2011
PT11VL02
Design
and Simulation of UART Serial Communication Module Based on VHDL
IEEE2011
PT11VL03
Reliable
and Cost Effective Anti-coll ision Technique for RFID UHF Tag
IEEE2011
PT11VL04
Reducing
the Computation Time in (Short Bit-Width) Two’s Complement Multipliers
IEEE2011
PT11VL05
High
Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree
IEEE2011
PT11VL06
An
Efficient Implementation of Floating Point Multiplier
IEEE2011
PT11VL07
An
On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic
Multiresolution
Supports for SoC
IEEE2011
PT11VL08
Radix-8
Booth Encoded Modulo Multipliers With Adaptive Delay for High
Dynamic Range
Residue Number System
IEEE2011
IEEE
2010
PT10VL01
A
Multibank Memory-Based VLSI Architecture of DVB
IEEE2010
PT10VL02
Implementation
of a Self-Motivated Arbitration Scheme for the Multilayer AHB Bus matrix
IEEE2010
PT10VL03
Low
Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of
GF 2M
IEEE2010
PT10VL04
LUT
Optimization for Memory-Based Computation
IEEE2010
PT10VL05
Improved
Area-Efficient Weighted Modulo 2n + 1
Adder Design With Simple Correction Schemes
IEEE2010
PT10VL06
New
Architectural Design of CA-Based Codec
IEEE2010
PT10VL07
An
Efficient 4-D 8PSK TCM Decoder Architecture
IEEE2010
PT10VL08
Design
Space Exploration of Hard-Decision Viterbi
Decoding: Algorithm and VLSI Implementation
IEEE2010
PT10VL09
On
Clustering of Undetectable Single Stuck-At Faults and Test Quality in
Full-Scan Circuits
IEEE2010
PT10VL10
Asynchronous
Data-Driven Circuit Synthesis
IEEE2010
PT10VL11
CORDIC
and SVD Implementation
in
Digital Hardware
IEEE2010
PT10VL12
Concept
and Development of Modular VLIW Processor Based on FPGA
IEEE2010
PT10VL13
Simple Traffic
Light Controller: A Digital Systems
Design
Project
IEEE2010
PT10VL14
FPGA
Implementation of Pipelined 2D-DCT and
Quantization
Architecture for JPEG Image
Compression
IEEE2010
PT10VL15
VHDL
SIMULATION OF PEAK DETECTOR, 64 BIT BCD COUNTER AND RESET AUTOMATIC BLOCK
FOR PD
DETECTION SYSTEM USING FPGA
IEEE2010
PT10VL16
A Harmonic
Signal Generator Based on DDS and SOPC
IEEE2010
PT10VL17
Design and
Implement of FFT Processor for OFDMA System Using FPGA
IEEE2010
PT10VL18
FPGA
Implementation Of Chaotic Cellular
Automaton with
Binary Synchronization Property
IEEE2010
PT10VL19
A New VLSI
Architecture of Parallel
Multiplier–Accumulator
Based on Radix-2
Modified Booth
Algorithm
IEEE2010
IEEE
2009
PT09VL01
Implementation
of Optimized 6-bit phase angle
calculation
from Phase gradients for T/R Modules in
Active Phased Array
Radars using FPGA
IEEE2009
PT09VL02
Power-Efficient
Pipelined Reconfigurable
Fixed-Width
Baugh-Wooley Multipliers
IEEE2009
PT09VL03
A
Spurious-Power Suppression Technique for
Multimedia/DSP
Applications
IEEE2009
PT09VL04
Multiplication
Acceleration Through Twin Precision
IEEE2009
PT09VL05
Efficient FPGA
implementation of convolution
IEEE2009
PT09VL06
A Low-Power Low-Area Multiplier Based on
Shift-and-Add Architecture
IEEE2009
PT09VL07
Spread
Spectrum Image Watermarking with Digital
Design
IEEE2009
PT09VL08
Left to Right Serial Multiplier for Large Numbers on
FPGA
IEEE2009
PT09VL09
A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box
Architecture
IEEE2009
PT09VL10
Power
Optimization of Linear Feedback Shift
Register
(LFSR) for Low Power BIST
IEEE2009
PT09VL11
Hardware
Algorithm for Variable Precision
Multiplication
on FPGA
IEEE2009
PT09VL12
A New High-Speed Architecture for Reed-Solomon Decoder
IEEE2009
PT09VL13
32-bit RISC CPU Based on MIPS
IEEE2009
BACK |
